Core Example Using Sparta

The Sparta core example is located in sparta/example/CoreModel.

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Example Core Layout

The CoreExample is an example Sparta simulator that uses the Sparta framework to mimic a very rudimentary model of a simple out-of-order core. The model does not have dependency checking nor actually renames any instructions. The "ISA" used is a few random instructions pulled from the PowerPC ISA listed in a table in Fetch.cpp.

For a more concrete core performance model, check out the RISC-V Performance Model based on Sparta: https://github.com/riscv-software-src/riscv-perf-model

The example touches on Sparta command line simulation, construction phasing, unit creation, port creation and binding, event creation, and data transfer.

The ExampleCore has a simple pipeline:

This heirarchy is built in core_example::ExampleSimulator::buildTree_ pulling resources and factories from core_example::CoreTopology_1.

Instructions are created in Fetch and progression of these instructions is based on a credit system. Credits flow from ROB through Dispatch though Rename, etc. in 0 time (dotted lines) while instructions flow from Fetch to Decode to Rename, etc (solid lines) in a delay of 1 cycle. This flow is controlled based on the rule (adopted by this example) that all DataInPorts<core_example::InstGroup> take objects delayed by 1 cycle (set at instantiation time) and all credit DataInPorts<uint32_t> are assumed to be 0 cycle. For example:

These ports are bound in core_example::ExampleSimulator::bindTree_, using the port_connections list defined in core_example::CoreTopology_1. The ports themselves are instantiated in Fetch.cpp / Fetch.hpp and Decode.cpp / Decode.hpp.

Without the delay of 1 cycle on the in_fetch_queue_write, we will come across a cycle in simulation:

Step.Time
   1.0    Fetch receive credits
   2.0    Fetch sends new instructions on the out port
   3.0    Decode would receive new instructions and process
   4.0    Decode send credits back to Fetch
   5.0    Goto 1?? Oops! Infinite loop!

Adding the cycle delay:

Step.Time
   1.0    Fetch receive credits
   2.0    Fetch sends new instructions on the out port
        ... delay
   1.1    Decode would receive new instructions and process
   2.1    Decode send credits back to Fetch
   3.1    Fetch receive credits
   4.1    Fetch sends new instructions on the out port
        ... delay, etc, etc

The entire core example follows this paradigm.

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Building

To build the CoreExample, simply type make in the example/CoreModel directory.

Refer to builtin help for up-to-date help and commands, but try running the model with the '-h' option.

% ./sparta_core_example -h
% ./sparta_core_example --verbose-help
% ./sparta_core_example --help-topic reporting

Most of the commands listed in the help are directly from the Sparta framework and not sparta_core_example. These are "free" commands the framework provides (via sparta::app::CommandLineSimulator). The modeler is not required to use this class for simulation.

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Invocations

Running/Configuring

Dump out the parameters:

% ./sparta_core_example --no-run \
                        --write-final-config-verbose params.yaml

Read in parameters from a file and/or change via the command line. Parameters are set in the order in which they are read from the command line.

% ./sparta_core_example -c params.yaml -p top.cpu.core?.fetch.params.num_to_fetch 2
 
  [in] Configuration: Node "" <- file: "params.yaml"
  [in] Configuration: Parameter "top.cpu.core?.fetch.params.num_to_fetch" <- value: "2"

Run for 1 million cycles, incrementing a ctr every 1000 cycles. Consume the config file test.yaml and produce a final yaml file called final.yaml. Also, dump the tree:

% ./sparta_core_example -r 1M \
                     --show-tree -p top.core0.params.ctr_incr_period 1000 \
                     -c test.yaml --write-final-config final.yaml

Debugging/Logging

Enable a Decode "info" log for 1,000 cycles.

% ./sparta_core_example -r 1K -l top.cpu.core?.decode info decode.out

Enable a Decode and Fetch "info" log for 1,000 cycles to the same file:

% ./sparta_core_example -r 1K -l top.cpu.core?.decode info fetch_decode.out \
                              -l top.cpu.core?.fetch  info fetch_decode.out

Enable a Decode and Fetch "info" log for 1K cycles after the first 100K cycles:

% ./sparta_core_example --debug-on 100K -r 101K \
                     -l top.cpu.core?.decode info fetch_decode.out \
                     -l top.cpu.core?.fetch  info fetch_decode.out

Enable a Decode and Fetch "info" log for 1K instructions after the first 100K instructions:

% ./sparta_core_example --debug-on-icount 100K -i 101K \
                     -l top.cpu.core?.decode info fetch_decode.out \
                     -l top.cpu.core?.fetch  info fetch_decode.out

Generating Reports

Refer to Report Definition Format (.rrep,.yaml) for more details on Reports.

Dump out a full, simple report report in html:

% ./sparta_core_example -r 1000000 --report-all output.html html
% ./sparta_core_example -r 1M --report-all output.html html  # Same command

Dump out a full, simple report with rules. The content is all inclusive of the entire simulation tree (the "" on the command line)

% cat simple_stats.yaml
content:
subreport:
  name: AUTO
  content:
    autopopulate: true
% ./sparta_core_example -r 1M --report "" simple_stats.yaml my_report.txt text

Dump out subset, but simple report with rules. The content is inclusive of the decode tree only for all cores:

% cat simple_stats.yaml
content:
subreport:
  name: AUTO
  content:
    autopopulate: true
% ./sparta_core_example -r 1M --report "top.cpu.core?.decode" simple_stats.yaml my_report.txt text

Create a ts_report.yaml file to dump out a time-series CSV report (must be run in example/CoreModel directory for the core_stats.yaml file). This is triggered on the stat total_number_retired reaching 3500 insts or greater. It's trigged "on" only once.

% cat > ts_report.yaml
content:
 
report:
  pattern:   top.cpu.core0
  def_file:  core_stats.yaml
  dest_file: core0.csv
  format:    csv
  trigger:
    start:   rob.stats.total_number_retired >= 3500
    update-time: 5 ns
 <ctrl-D>
 % ./sparta_core_example -r 1M --report ts_report.yaml

Generating Pipeouts

Refer to https://github.com/sparcians/map/tree/master/helios/pipeViewer for directions on building/installing the MAP::Helios::Argos tools preferably using the Conda tools.

Create a 10K instructions Pipeout:

% pwd
$HOME/map/sparta/build/example/CoreModel
% ./sparta_core_example -i10K -z my_pipeout

This will create a set of files for the Argos viewer:

% ls -1 my_pipeout*
my_pipeoutclock.dat
my_pipeoutdata.dat
my_pipeoutdisplay_format.dat
my_pipeoutindex.bin
my_pipeoutlocation.dat
my_pipeoutmap.dat
my_pipeoutrecord.bin
my_pipeoutsimulation.info
my_pipeoutstring_map.dat

Launch the MAP::Helio::Argos viewer (this assumes the correct tools/libaries have been installed). Note that the cpu_layout.alf file is NOT in the build directory of the CoreModel.

% pwd
$HOME/map/sparta/build/example/CoreModel
% python3 $HOME/map/helios/pipeViewer/pipe_view/argos.py \
       -l $HOME/map/sparta/example/CoreModel/cpu_layout.alf \
       -d my_pipeout

The view that pops up is a single-cycle view of the CPU.