The Sparta Modeling Framework
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gen_layouts.py
1import sys,os
2import pathlib
3
4
5gen_dir = pathlib.PurePath(os.path.abspath(__file__))
6scripts_dir =''
7alf_gen_path = '/helios/pipeViewer/scripts'
8for part in gen_dir.parts[1:]:
9 scripts_dir += '/' + part
10 if os.path.exists(scripts_dir + alf_gen_path):
11 scripts_dir += alf_gen_path
12 break
13assert scripts_dir != '', f"Can't find {alf_gen_path}"
14
15sys.path.append(scripts_dir)
16from alf_gen.ALFLayout import ALFLayout
17
18if os.path.isfile("pipeout/location.dat") == False:
19 print('''ERROR: Cannot find pipeout/location.dat. This tool cannot be run without a location file.
20 To generate one:
21 mkdir pipeout
22 ./sparta_core_example -i1 -z pipeout/
23 ''')
24 exit(255)
25try:
26 os.mkdir('layouts')
27except:
28 pass
29
30NUM_CYCLES = 55
31layout = ALFLayout(start_time = -10,
32 num_cycles = NUM_CYCLES,
33 clock_scale = 1,
34 location_file = "pipeout/location.dat",
35 alf_file = "layouts/cpu_layout.alf")
36
37general_height = 15
38layout.setSpacing(ALFLayout.Spacing(height = general_height,
39 height_spacing = general_height - 1,
40 melem_height = general_height/3,
41 melem_spacing = general_height/3 - 1,
42 caption_width = 150))
43
44sl_grp = layout.createScheduleLineGroup(default_color=[192,192,192],
45 include_detail_column = True,
46 margins=ALFLayout.Margin(top = 2, left = 10))
47
48# Fetch
49sl_grp.addScheduleLine('.*fetch.next_pc', ['Next PC'], space=True)
50
51# Decode
52sl_grp.addScheduleLine('.*decode.FetchQueue.FetchQueue([0-9]+)', [r'FQ[\1]'], space=True)
53
54# Rename
55sl_grp.addScheduleLine('.*rename.rename_uop_queue.rename_uop_queue([0-9]+)', [r'Rename[\1]'], space=True)
56
57# Dispatch
58sl_grp.addScheduleLine('.*dispatch.dispatch_queue.dispatch_queue([0-9]+)', [r'Dispatch[\1]'], mini_split=[80,20], space=True)
59
60# Credits
61sl_grp.addScheduleLine('.*dispatch.in_(.*)_credits', [r'\1 Credits'], space=True, nomunge=True)
62
63# ALUs
64def add_exe_block(block_name):
65 num_block_names = layout.count(f'(.*{block_name}[0-9]+)\..*')
66 if num_block_names == 0:
67 sl_grp.addScheduleLine(f'.*{block_name}.scheduler_queue.scheduler_queue([0-9]+)',
68 [rf'{block_name} IQ\1 '], space=True)
69 sl_grp.addScheduleLine(f'.*{block_name}$', [rf'{block_name} pipe'], space=True)
70 else:
71 cnt = 0
72 while cnt < num_block_names:
73 sl_grp.addScheduleLine(f'.*{block_name}{cnt}.scheduler_queue.scheduler_queue([0-9]+)',
74 [rf'{block_name}{cnt} IQ\1 '], space=True)
75 sl_grp.addScheduleLine(f'.*{block_name}{cnt}$', [rf'{block_name}{cnt} pipe'], space=True)
76 cnt += 1
77
78for block in ['alu', 'fpu', 'br']:
79 add_exe_block(block)
80
81# LSU
82sl_grp.addScheduleLine('.*lsu.lsu_inst_queue.lsu_inst_queue([0-9]+)', [r'LSU IQ[\1]'])
83sl_grp.addScheduleLine('.*lsu.LoadStorePipeline.LoadStorePipeline([0-9]+)',
84 ['LSU Pipe MMU',
85 'LSU Pipe D$',
86 'LSU Pipe Commit'], reverse=False)
87sl_grp.addScheduleLine('.*lsu.dcache_busy$', ['D$ Busy'], nomunge=True, space=True)
88
89# ROB
90sl_grp.addScheduleLine('.*rob.ReorderBuffer.ReorderBuffer([0-9])', [r'ROB[\1]'], mini_split=[80,20], space=True)
91
92# Insert the cycle line
93sl_grp.addCycleLegend(ALFLayout.CycleLegend(location = 'top.cpu.core0.rob.ReorderBuffer.ReorderBuffer0',
94 interval = 5))
95
96col_view = layout.createColumnView(margins=ALFLayout.Margin(top=2, left=1000),
97 content_width=500)
98col_view.addColumn('.*rob.ReorderBuffer.ReorderBuffer([0-9]+)', [r'ROB[\1]'])